1. Field of the Invention
The present invention relates to a row decoder circuit of a NAND flash memory device and method of supplying an operating voltage using the same. More specifically, the present invention relates to a row decoder circuit of a NAND flash memory device and method of normally supplying an operating voltage using the same to a wordline or a selected line during a low power operation.
2. Discussion of Related Art
A NAND flash memory device is a type of storage apparatus that is electrically erasable and programmable, retaining its data even without a power supply. Such a NAND flash memory device is configured according to the following structure.
FIG. 1 is a block diagram showing a general NAND flash memory device.
As illustrated in FIG. 1, the NAND flash memory device includes a memory cell array 110, a row selection circuit 120, and a page buffer circuit 130.
The memory cell array 110 includes pluralities of strings 111 coupled to bitlines BL0˜BLm respectively. The string 111 on each column (or bitline) is composed of a drain selection transistor DST, a source selection transistor SST, and pluralities of flash memory cells MCn (n=0˜15; shown with 16 in number as an example) serially connected between the selection transistors DST and SST. The drain selection transistor DST on each column has a drain connected to the bitline and a gate coupled to a drain selection line DSL. The source selection transistor SST has a source connected to a common source line CSL and a gate coupled to a source selection line SSL. Between a source of the drain selection transistor DST and a drain of the source selection transistor SST, the flash memory cells M15˜MC0 are connected in series. The flash memory cells MC15˜MC0 are each coupled to wordlines WL15˜WL0.
Meanwhile, the drain selection line DSL, the wordlines WL0˜WL15, and the source selection line SSL are electrically connected to the row selection circuit. The row selection circuit 120 selects one of the wordlines in response to address information, and supplies wordline voltages to selected and deselected wordlines in accordance with each operation mode, which will be described later in detail.
The bitlines BL0˜BLm arranged on the memory cell array 110 are each connected to pluralities of page buffers included in the page buffer circuit 130. The page buffer circuit 130 senses data from the flash memory cells coupled to selected wordlines in a read mode through the bitlines BL0˜BLm, and supplies a power source voltage or a ground voltage to the bitlines BL0˜BLm in correspondence with data to be programmed.
The row selection circuit 120 supplies a program voltage (e.g., 18V) to a selected wordline, during a program mode, while supplying a pass voltage (e.g., 10V) to deselected wordlines. The row selection circuit 120 supplies the ground voltage to a selected wordline, during a read mode, while supplying a read voltage (e.g., 4.5V) to deselected wordlines. The program voltage, the pass voltage, and the read voltage are voltages (e.g., 3V) higher than the power source voltage.
In order to supply a high voltage over the power source voltage to the wordline in response to the address information, the row selection circuit 120 is required to include a circuit capable of switching the high voltage. Such a high-voltage switching circuit may be implemented by means of a switch pumping or boosting scheme.
FIG. 2 is a circuit diagram illustrating the row selection circuit shown in FIG. 1.
Referring to FIG. 2, the row selection circuit 120 includes a decoding block 121, a switch pumping block 122, and a switching block 123.
The decoding block 121 may be constructed of NAND gates G1 and G2. Address signals DA1˜DAi are applied to the first NAND gate G1, while a control signal BLKWLdis and an output signal of the first NAND gate G1 are applied to the second NAND gate G2. The control signal BLKWLdis is held at a high level while prosecuting erasing, programming, and reading operations.
The switch pumping block 122 is connected to a block wordline node BLKWL, and is constructed of a third NAND gate 63, a capacitor C1, and first through fourth NMOS transistors MN1˜MN4, as illustrated in FIG. 2.
The switching block 123 is composed of pass (or transfer) transistors, NDSL, N15˜N0, and NSSL, which transfer selection signals, GDSL, GWL15˜GWL0, and GSSL, to their corresponding signal lines DSL, WL15˜WL0, and SSL. The pass transistors, NDSL, N15˜N0, and NSSL, are coupled to the block wordline node BLKWL through their gates.
The decoding block 121 and the switch pumping block 122 construct a block decoder to select a memory block.
When at least one of the address signals DA1˜DAi is low level, an output signal of the decoding block 121 goes to low level. During this, the switch pumping block 123 does not prosecute a pumping operation of a clock signal CLK. Otherwise, when the address signals DA1˜DAi are all at a high level, the output signal of the decoding block 121 goes to a high level. The switch pumping block 122 operates in response to the low-to-high and the high-to-low transitions of the clock signal CLK. Here, the low level is the ground voltage level and the high level is the power source voltage level. The capacitor C1 repeats charging/discharging operations in accordance with the transitions of the clock signal CLK. If the capacitor C1 is charged up with pumped charges by the high-to-low transitions of the clock signal CLK, the pumped charges are transferred through the first NMOS transistor MN1 to increase a voltage of the block wordline node BLKWL.
If the clock signal CLK transitions to high level from low level, a VPP voltage (a read voltage Vread in a reading operation, a program voltage Vpgm in a programming operation; hereinafter, referred to as ‘operating voltage’) is supplied to a gate of the second NMOS transistor MN2. The second NMOS transistor MN2 is conditioned into a shut-off state by a voltage difference between the gate and source after some time.
If the capacitor C1 is charged up again by the high-to-low transition of the clock signal CLK, pumped charges are transferred through the first NMOS transistor MN1 to increase the voltage of the block wordline node BLKWL. Thereafter, if the clock signal CLK transitions to high level from low level, the operating voltage is applied to a gate of the first NMOS transistor MN1 through the second NMOS transistor MN2. By the repetition of this operation, the voltage of the block wordline node BLKWL gradually increases to reach VPP0+Vtn3 finally. Here, Vtn3 is a threshold voltage of the third NMOS transistor MN3. The third NMOS transistor MN3 clamps the voltage of the block wordline node BLKWL that may increase over a required voltage level.
By way of the operation described above, the block wordline node BLKWL has a voltage level that is high enough to transfer the program voltage Vpgm or the read voltage Vread to a corresponding wordline.
However, the structure of the switch pumping block shown in FIG. 2 is inadequate for a low-power NAND flash memory device in the following reason.
While performing the pumping operation, the threshold voltage of the first and second NMOS transistors MN1 and MN2 are raised by body effects. As a result, the voltage level of the block wordline node BLKWL is limited to increasing due to the rising threshold voltages.
A problem of the conventional row selection circuit during a programming operation will be described with reference to waveforms at the nodes.
FIG. 3 is a waveform diagram illustrating potentials of nodes in the row selection circuit during a programming operation.
Referring to FIGS. 2 and 3, transfer of a Vcc voltage of GDSL, and Vpgm and Vpass of GWL0˜GWL15 to the drain selection line DSL and the wordlines WL0˜WL15 without voltage drops by Vth is only possible when the voltage of the block wordline node BLKWL is equal to or higher than Vpgm+Vth.
But, there is degradation of pumping efficiency due to the rising threshold voltage by body effects at the first and second NMOS transistors MN1 and MN2 used in the switch pumping block 122. Especially, in the condition of pumping under a low Vcc, the pumping efficiency is almost insignificant.
Therefore, in a pumping operation under the low Vcc, it is impossible to transfer the program voltage, as well as the pass voltage, because the voltage of the block wordline node BLKWL does not rise up to Vpgm+Vth.